Charging a capacitive load from a voltage source invokes a ½ CV2 energy penalty. The concept of adiabatic charging, where the capacitor is charged more slowly than nominally afforded by the natural RC time constant of the charging circuit in the pursuit of reducing energy dissipation to below ½ CV2, has been contemplated for decades. Despite the interest in adiabatic charging, there has not been any solution to enabling this slow charging phenomenon in a practical, low-overhead charging circuit. For example, prior work used separate DC-DC converters to provide multiple voltage levels, or used resonant inductors, both of which invoke significant area overhead.
Capacitive load charging consumes a significant amount of power budget in system-on-a-chip (SoC) systems. As an example, clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactance of global clock networks at a given resonance frequency, fo, have been proposed. Conventionally, such schemes are only suitable at high multi-GHz frequencies in order to be able to place the employed inductors on chip. See, e.g. S. Chan et al., “A 4.6 GHz Resonant Global Clock Distribution Network,” ISSCC Dig. Tech. Papers, 2004; P. Restle et al., “Wide-Frequency-Range Resonant Clock with On-The-Fly Mode Changing for the POWER8™ Microprocessor,” ISSCC Dig. Tech. Papers, 2014.
Since many modern energy-efficient SoC designs optimize for clock frequencies <2 GHz, with DVFS (Dynamic Voltage and Frequency Scaling) techniques bringing the core clock frequencies and the supply voltages VDD to the MHz and near-threshold regimes, respectively, there is a need to develop low-power clock distribution schemes that can work across increasingly wider operating ranges. While recent work in quasi-continuous resonant clocking have been proposed to intermittently cancel global clock tree capacitance during edge transitions, such techniques require large off-chip inductors and are limited to 0.98 MHz [H. Fuketa et al., “Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for 0.37v 980 khz Near-Threshold Logic Circuits,” ISSCC Dig. Tech. Papers, 2013] and 150 MHz [F. Rahman et al., “Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System,” ISSCC Dig. Tech. Papers, 2016], respectively, because of the need to operate well below resonance (i.e., <<fo/10). Thus, while prior approaches have shown power reduction for targeted applications, these prior approaches all require large on- or off-chip magnetics, and do not meet the MHz-to-GHz frequency-range needs of modern DVFS-enabled SoCs.
FIGS. 1A-1C illustrate prior resonant clocking techniques, respectively including resonant clocking [Chan et al., supra; Restle et al., supra] intermittent resonant clocking (IRC) [Fuketa et al. supra] and quasi-resonant clocking (QRC) [Rahman et al., supra]. Such conventional approaches utilize an array of on-chip inductors (represented by the inductor in FIG. 1A) along with per-inductor decoupling capacitor (>10× CCLK). Unfortunately, CLK power increases ˜±20% away from resonance (fo), thereby limiting DVFS opportunities. On the other hand, IRC and QRC techniques can enable DVFS up to ˜fo/10 by employing large off-chip inductors (represented by the inductor in each of FIGS. 1B and 1C). However, such approaches can have severe ringing if accurate pulse width timing is not ensured, thereby requiring power-expensive timing logic overhead (e.g., delay-locked-loops, DLLs). Furthermore, special gate drivers or charge pumps are required to either boost the gate drive voltage of the footer NMOS in IRC techniques, or provide a −VDD/2 gate drive for QRC footer transistor Mf, to ensure that it turns off before its drain voltage goes to −VDD/2 (which is a further device reliability issue).